Runtime Verification of Transaction Level SystemC Models using an Aspect-based Approach

Assertion-Based Verification of Transaction Level Models

Transaction Level Modeling with SystemC has become a de-facto industry standard for modeling of system-on-chip designs. The correctness of these models is therefore of crucial importance. In this paper, we propose a novel methodology to apply AssertionBased Verification to Transaction Level Models. The novelty is based on two contributions: (1) Using Aspect-Oriented Programming techniques permi...

Dynamic Verification of SystemC with Statistical Model Checking

Transaction-level modeling with SystemC has been very successful in describing the behavior of embedded systems by providing high-level executable models, in which many of them have an inherent probabilistic behavior, i.e., random data, unreliable components. It is crucial to evaluate the quantitive and qualitative analysis of the probability of the system properties. Such analysis can be condu...

Runtime verification of programs using rule-based active system

Reactivity in SystemC Transaction-Level Models

SystemC is a popular language used in modeling systemon-chip implementations. To support this task at a high level of abstraction, transaction-level modeling (TLM) libraries have been recently developped. While TLM libraries are useful, it is difficult to capture the reactive nature of certain transactions with the constructs currently available in the SystemC and TLM libraries. In this paper, ...

A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection Processes

Newly emerging safety standards are driving system-on-chip manufacturers to develop better errordetection and correction mechanisms as well as verification environments for their systems. Fault injection in models is one enhancement for verification environments with which chip aging and safety-critical features (e.g., resilience against radiation sensitivity) are verified. SystemC offers the a...